Rajkumar Sarma

Dr Sarma’s research focuses on automated transistor-level and digital IC design, low-power design, FPGA prototyping, and machine learning–driven EDA automation. At Lero, he contributed extensively to the Automatic Design of Digital Circuits (ADDC) project, where he helped develop ML-based systems for autonomous hardware generation. His work includes building a Grammatical Evolution–based HDL code generator and transistor-level circuit generator in Cadence SKILL. He is currently a collaborator on Enterprise Ireland’s Commercialisation Fund project AutoCircuit, which aims to advance end-to-end automation for digital IC design.

He has strong expertise in Cadence design tools (Virtuoso, Assura, Genus, Innovus, JasperGold Superlint) and FPGA development using AMD Xilinx ISE/Vivado on 7-series boards. Dr Sarma played a key role in achieving the world’s first ML-generated ASIC, validated on FPGA and fabricated using TSMC 65 nm technology. His responsibilities included FPGA realization, SPI interfacing, synthesis, physical implementation, and functional testing of silicon chips.

Dr Sarma has authored multiple publications in reputable journals and conferences, including Neural Computing and Applications (NCAA), Algorithms, and CMC: Computers, Materials & Continua. He is also the author of four books related to HDL, FPGA prototyping, and VLSI design. His research innovations have led to multiple patent applications, including a granted patent on a Signed Floating-Point MAC Architecture by the Indian Patent Office.

With more than 13 years of teaching and research experience, Dr Sarma has supervised numerous postgraduate and undergraduate students, many of whom have progressed into roles within the IC design and semiconductor industry. His teaching and research continue to advance automated EDA workflows, energy-efficient architectures, and next-generation hardware design methodologies.