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Andrew Anderson

Senior Research Fellow

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Trinity College Dublin

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I’m currently a Senior Research Fellow in the School of Computer Science and Statistics at TCD. My work focuses mainly on the design, and uses, of compiler technology.

I’m particularly interested in domain-specific code generation. In a nutshell, replacing generic libraries of hand-written code with tools that instead generate very good specialized code for a given instance of a problem from some domain. I’ve worked on code generation for vectorization, and domain-specific code generation for fast custom precision arithmetic, both floating-point and integer, and for deep learning.

  • Publications
2020
Anderson A, Vasudevan A, Keane C, Gregg D.  2020.  High-Performance Low-Memory Lowering: GEMM-based Algorithms for DNN Convolution. 2020 IEEE 32nd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD).
Barabasz B, Anderson A, Soodhalter KM, Gregg D.  2020.  Error Analysis and Improving the Accuracy of Winograd Convolution for Deep Neural Networks. ACM Trans. Math. Softw.. 46
Wen Y, Anderson A, Radu V, O'Boyle M, Gregg D.  2020.  TASO: Time and Space Optimization for Memory-Constrained DNN Inference. 2020 IEEE 32nd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD).
2019
Persand K, Anderson A, Gregg D.  2019.  A Taxonomy of Channel Pruning Signals in CNNs. CoRR. abs/1906.04675
2018
Anderson A, Gregg D.  2018.  Scalar Arithmetic Multiple Data: Customizable Precision for Deep Neural Networks. CoRR. abs/1809.10572
Barabasz B, Anderson A, Gregg D.  2018.  Improving accuracy of Winograd convolution for DNNs. CoRR.
Anderson A, Gregg D.  2018.  Optimal DNN Primitive Selection with Partitioned Boolean Quadratic Programming. Proceedings of the 2018 International Symposium on Code Generation and Optimization.
2017
Vasudevan A, Anderson A, Gregg D.  2017.  Parallel Multi Channel convolution using General Matrix Multiplication. 2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP)2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP).
Anderson A, Muralidharan S., Gregg D.  2017.  Efficient Multibyte Floating Point Data Formats Using Vectorization. IEEE Transactions on Computers. 66:2081-2096.
2016
Anderson A, Gregg D.  2016.  Vectorization of Multibyte Floating Point Data Formats. Proceedings of the 2016 International Conference on Parallel Architectures and Compilation.

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